`include "master_interface.v"
`include "slave_interface.v"
`include "handshake_pipe.v"

module SimTop (

    input  wire clk,
    input  wire rst,

    input  wire        master_en,
    input  wire [31:0] master_data,
    output wire        master_busy,


    output wire        slave_en,
    output wire [31:0] slave_data,
    input  wire        slave_busy
    );
    
    wire [31:0] master_data_reg, reg_data_slave;
    wire master_valid_reg, reg_valid_slave;
    wire master_ready_reg, reg_ready_slave;
    
    master_interface master_interface_inst(
        .clk(clk),
        .rst(rst),

    //input signals
        .i_master_data(master_data),
        .i_master_en  (master_en),
        .o_master_busy(master_busy),

    // signals to slave
        .o_master_data (master_data_reg),
        .o_master_valid(master_valid_reg),
        .i_master_ready(master_ready_reg)
    );

    handshake_pipe handshake_pipe_inst (
        .clk(clk),
        .rst(rst),

        .master_valid(master_valid_reg),
        .master_data (master_data_reg ),
        .master_ready(master_ready_reg),

        .slave_valid (reg_valid_slave ),
        .slave_data  (reg_data_slave  ),
        .slave_ready (reg_ready_slave )
    );


    slave_interface slave_interface_inst (
        .clk(clk),
        .rst(rst),


    // output signals
        .o_slave_data(slave_data),
        .o_slave_en  (slave_en  ),
        .i_slave_busy(slave_busy),

    // signals between master and slave interfaces
        .i_slave_valid(reg_valid_slave),
        .i_slave_data (reg_data_slave ),
        .o_slave_ready(reg_ready_slave)
    );
endmodule